1. Field of the Invention
The present invention relates generally to a branch instruction control system and more specifically to a branch instruction address calculating circuit incorporated in a processor of an advance control method or pipe line processing method.
2. Description of the Prior Art
In up-to-date microprocessors, an advance control method (pipe line processing method) has been adopted to increase the processing speed. In the pipe line processing method, the processing of an instruction is divided into several stages; each divided instruction is processed at each stage in parallel; and further the succeeding instruction to be processed next is read or decoded when the current instruction is being executed at each stage (referred to as advance control).
In the above-mentioned microprocessor for an advance control method, a target branch address of a branch instruction is first calculated, and then the branch instruction (jumping instruction) is executed.
In the prior art branch instruction control system, however, since the branch address is calculated after the branch instruction has reached the execution step, it takes a long execution time for the branch instruction processing and thus the processing speed of the processor is reduced.
The configuration of the prior art branch instruction control system will be described in further detail hereinafter with reference to FIG. 1 under DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT.